Video Processing with Zynq

i. Video Processing with Zynq: Resources

This Tutorial series covers the Video Processing Fundamental’s and Project’s with Xilinx Zynq 7000 and Zynq Ultrascale+MPSoC  FPGA.

Here are the some Test Output of TPG [Test Pattern Generator] IP Implementation on VIVADO IP integrator and SDK configuration for Processing System for TPG.

Figure: Remapping the TPG output on Xilinx Zynq FPGA [Computer Vision Appliction]

Tutorial’s on Video Processing with Zynq:

  1.  TPG interfacing with Zynq
  2. AXI VDMA Interfacing and Configuring: AXI-VDMA and AXI Video Processing Resources
  3. Creating Custom High Level Synthesis [HLS] IP for Computer Vision: Sobel, Dilation, Harris Corner, Canny , Remap etc.

More Video Tutorial/Session’s are coming up soon!


Do you want to Learn “Video Processing with FPGA’s?”

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Course Detail’s:

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ii.Featured Video tutorial on “Video Processing with Zynq

a. Test Pattern Generator and VDMA IP implementation on Zynq based design

b. Video DMA (VDMA) configuration with Xilinx VIVADO SDK

c. Test Pattern Generator (TPG) implementation demo on Zynq FPGA Board, ZedBoard FPGA


iii. Tutorials from our past project  on Video Processing with Zynq:

a. Real time video overlay and mixing with Xilinx Zynq FPGA [ZedBoard FPGA]

b. Multi-channel Video Overlay with Zynq FPGA

c. Real time Video Encryption/Decryption with AES algorithm on Zynq FPGA

For more details, please write us at: or

#video #processing #zynq #fundamental #TPG #ZedBoard #FMC #ZC702 #Zybo #FPGA #computer #vision #remap #sobel #xilinx #MPSoC #ultrascale+