While working on the X16r Crypto Algorithm targeting the VCU1525/CVP13 FPGA with MUX based design as many FPGA developer faced the challenge of large fluctuation on the hash rate; we also face that issue of hash high dropdown. So we Design our X16r on Partial Reconfiguration.
What is Partial Reconfiguration (PR) on FPGA?
Partial reconfiguration is the design flow on FPGA by which user can change some of the logic or functionality on some section of FPGA while other sections are running at the moment. So the Partial Reconfiguration specially the Dynamic Partial Reconfiguration allow to change the bitstream on the specific region [Reconfigurable Region] while other regions are working on different bitstream!
As of this feature large number of bitstream generated from the PR flow for X16r can be implemented on the VCU1525 or CVP13 FPGA.
Partial Reconfiguration is supported by Xilinx Ultrascale+, Ultrascale and 7 series of FPGA. While the Partial Reconfiguration is also supported on Intel-Altera and other FPGA vendor based FPGA/tools.
Resources on Partial Reconfiguration from LogicTronix
Want to learn more on Partial Reconfiguration?
As of our “Democratizing FPGA Education all over the World” initiative, we have released the Ultra Low Cost Course on “Partial Reconfiguration (PR) with FPGA”. Some of the Features of Course: -Learn PR Flow , Implement the PR design on FPGA, Debug PR design and Implement PR flow with PCIe and Processing Unit.
From the Course you will learn:
- Partial Reconfiguration Design Flow
- Xilinx VIVADO tool and FPGA devices for Partial Reconfiguration Flow
- Debugging the PR Design with ILA and VIO
- Using PR Controller with VIVADO IP platform and FPGA
- Using Microblaze and PCIe on PR flow
- Bitstream Relocation Methodology
Join the Course: Ultra Low Cost [$9.99] Coupon Code Link